The present invention relates to semiconductor design. More specifically, the present invention relates to methods and systems for verifying semiconductor designs using hardware description language.
When designing an integrated circuit device it is desirable to test the integrated circuit by inputting signals and determining if the correct output signal is generated. This can occur both on externally available signal locations (such as the pins of an integrated circuit) and internally within the integrated circuit. Within an integrated circuit, areas of an integrated circuit can be divided into “blocks.” It is then determined if signals travel to and from various blocks within a specified design time. This can be called connectivity verification because one is determining whether each block within the integrated circuit device is correctly connected to other blocks within the integrated circuit device. A “trace bus” is a common logic component verified using connectivity verification, propagation certain signals of a chip to certain endpoints where they can be read to on-chip evaluation circuits or even read out of the chip for analysis.
Connectivity verification is often decomposed into two portions fail verification and cover verification. Fail verification checks for the correct propagation of signals under a specified mode condition. Cover verification checks for the ability to initialization logic to sensitize a given mode condition. While decomposing connectivity verification into two portions enables greater scalability, it can become time consuming because it requires two different checks to occur. Issues also can occur when one signal is present in the cone of influence of another signal being checked.